In integrated circuits operated synchronously with an input signal applied to the circuit externally, for example, with an externally applied clock signal, an internal signal derived from the external input signal is generally generated. Control operations are controlled synchronously with the internal signal internally within the circuit. In this case, the internal signal must be generated clock-synchronously with the external input signal. For synchronizing the external input signal with an internal signal, it is possible to use, for example, a delay circuit shown in FIG. 1, a so-called DLL (delay lock loop) circuit. The DLL circuit generates an output signal that is derived from an input signal and behaves phase-synchronously with respect to the latter.
FIG. 1 shows an integrated circuit comprising a delay circuit of this type. An input signal IN, which can be a clock signal, for example, is applied to an input terminal E0 of the integrated circuit. The input signal IN is amplified by a receiving circuit 1 and fed as a signal CK to an input terminal E10 of a delay circuit. The input terminal E10 is connected to a controllable delay device 2. After a delay of the signal CK in the controllable delay device, a signal P that is phase-shifted with respect to the signal CK is generated at an output terminal A10. The phase-shifted signal P is amplified via a driver circuit 3 and output as signal OUT at an output terminal A0 of the integrated circuit. The input signal IN experiences a respective delay τ1 and τ3 in the receiving circuit 1 and the driver circuit 3. The delay τ2, with which the input signal CK is delayed in the controllable delay device 2, can be set via a control signal CTRL.
In order that the output signal OUT is generated phase-synchronously with respect to the input signal IN, the delay time τ2 of the controllable delay device 2 must be set such that the input signal IN experiences, in the forward path comprising the receiving circuit 1, the controllable delay device 2 and the driver circuit 3, a delay corresponding to a multiple of the clock period of the input signal IN.
For setting the delay time τ2 of the controllable delay device 2, the phase-shifted signal P is fed to a feedback circuit 4 and delayed there by a time TC, in which the delay time τ1 of the receiving circuit 1 and the delay time τ3 of the driver circuit 3 are taken into account. The signal CK generated by the receiving circuit 1 on the output side and a signal FB generated by the feedback circuit on the output side are subsequently fed to a phase detector 5. The phase detector 5 compares the phase of the signal CK with the phase of the signal FB and generates a comparison signal VS on the output side, the comparison signal being fed to a control circuit 6. Depending on the comparison signal VS, the control circuit 6 generates the control signal CTRL, which can be used to set the delay time τ2 of the controllable delay device 2. Via the control loop of the delay circuit, the delay time of the delay device 2 is in this case varied such that the phase of the signal CK matches the phase of the signal FB at the phase detector 5. In this case the circuit is in a locked state.
FIGS. 2A, 2B and 2C in each case show a schematic illustration of the delay device 2. The delay device comprises a chain of delay elements, wherein each delay element delays the input signal CK by a delay time t. Depending on the set delay time or the control signal CTRL with which the controllable delay device is driven, the phase-shifted signal P that is delayed with respect to the signal CK is tapped off downstream of a delay element of the chain and fed, in accordance with FIG. 1, to the output terminal A0 of the delay circuit.
In the case of FIG. 2A, an input signal having a frequency f0 is fed to the delay circuit. In order to generate the output signal of the delay circuit phase-synchronously with respect to the input signal, the signal CK fed to the delay device is output from the delay device in a manner delayed by a delay time t1. In order to generate the output signal phase-synchronously with respect to the input signal, the input signal can also be coupled out from the delay device after a delay time t9, since the delayed signal has the same phase, a rising edge in the example in FIG. 2A, at this instant as at the delay instant t1. The delay device 2 is generally set with the lowest delay time, the delay time t1 in the example of FIG. 2A, by the control circuit 6.
In the event of the frequency of the input signal being increased to a frequency f1, the delay time of the controllable delay device is reduced by the control loop of the DLL circuit. As is illustrated in FIG. 2B, at the increased frequency f1, the signal fed to the controllable delay device is already coupled out from the delay device after a delay time t0.
If the frequency of the input signal is increased even further to a frequency f2, however, the phase-shifted signal P with the required phase, for example, a rising edge, can no longer be coupled out earlier from the delay device since the phase-shifted signal P has already been coupled out from the delay device at the earliest possible delay instant t0 at the frequency f1. In order to generate an output signal phase-synchronously with respect to the input signal also at the higher frequency f2 of the input signal, a further controllable delay device must be provided.
In the method illustrated in FIGS. 2A to 2C, the maximum delay time tmax which can be set via the controllable delay device should be chosen such that the maximum possible delay time tmax corresponds to the period duration of the lowest possible frequency of the input signal, for example, the lowest specified frequency. Owing to the necessary length of the delay chain for synchronizing low frequencies of an input signal and the necessity of having to provide a second delay circuit at high frequencies of the input signal, a large area and a high current are required on a chip of an integrated circuit, for example on a chip of an integrated semiconductor memory.